1. Field of the Invention
The present invention relates to an image data processing apparatus or system for executing processings of image data such as extraction, deletion, synthesization or the like types of processing. The image processor system of this type is useful as image or picture editing means and is applicable to character reading and, sign collating pattern recognition processing systems.
2. Description of the Prior Art
A major part of the image processing is a repetition of a series of processings mentioned below:
(1) Calculation of address of desired image data in a memory. PA1 (2) Reading of one word of the desired image data or information from the memory. PA1 (3) Processing of one word of the image data read out from the memory. PA1 (4) Calculation of the memory address at which the processed image data of one word is to be stored. PA1 (5) Writing of the processed image data of one word.
In a known image data processing system, the series of processings mentioned above are executed by a single processing unit, as is disclosed in Japanese Patent Application Laid-Open No. 67445/1981. As a consequence, the address calculation, memory access and the processing of the image data are performed in a serial fashion, requiring considerable time for completing the whole processings. Among the series of processings mentioned above, the address calculation is mainly accomplished by arithmetic operation on a number of bit positions in parallel, while the processing of the image data is carried out by arithmetic operation on the individual bits sequentially. A great degree of difficulty has previously been encountered in implementing a processor which is capable of performing both types of the processings mentioned above effectively at a high speed.